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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21381-1E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F74UV
s DESCRIPTION
The Fujitsu MB15F74UV is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the 2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation. The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial date. The serial data format is the same as MB15F74UL. Fast locking is achieved for adopting the new circuit. MB15F74UV is in the small package (BCC18) which decreases a mount area of MB15F74UV about 50% comparing with the former BCC20 (for dual PLL) .
s FEATURES
* High frequency operation : RF synthesizer : 4000 MHz Max : IF synthesizer : 2000 MHz Max * Low power supply voltage : VCC = 2.7 V to 3.6 V * Ultra low power supply current : ICC = 9.0 mA Typ (VCC = 3.0 V, Ta = +25 C, SWIF = SWRF = 0 in IF/RF locking state) (Continued)
s PACKAGE
18-pin plastic BCC
(LCC-18P-M05)
MB15F74UV
(Continued) * Direct power saving function : Power supply current in power saving mode Typ 0.1 A (VCC = 3.0 V, Ta = +25 C at 1 system) Max 10 A (VCC = 3.0 V at 1 system) * Software selectable charge pump current : 1.5 mA/6.0 mA Typ * Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65) * 23 bit shift register * Serial input binary 14-bit programmable reference divider : R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 3 to 2,047 * Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit * On-chip phase control for phase comparator * On-chip phase comparator for fast lock and low noise * Built-in digital locking detector circuit to detect PLL locking and unlocking * Operating temperature : Ta = -40 C to +85 C * Serial data format compatible with MB15F74UL * Ultra small package BCC18 (2.4 mm x 2.7 mm x 0.45 mm)
s PIN ASSIGNMENTS
TOP VIEW
Clock OSCIN Data GND finIF XfinIF GNDIF VCCIF DOIF 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 LE finRF XfinRF GNDRF VCCRF DORF
PSIF PSRF LD/fout
(LCC-18P-M05)
2
MB15F74UV
s PIN DESCRIPTION
Pin no. 1 2 3 4 5 6 7 Pin name GND finIF XfinIF GNDIF VCCIF DoIF PSIF I/O I I O I Descriptions Ground pin for OSC input buffer and the shift register circuit. Prescaler input pin for the IF-PLL. Connection to an external VCO should be AC coupling. Prescaler complimentary input for the IF-PLL section. This pin should be grounded via a capacitor. Ground pin for the IF-PLL section. Power supply voltage input pin for the IF-PLL section, the shift register and the oscillator input buffer. Charge pump output for the IF-PLL section. Power saving mode control pin for the IF-PLL section. This pin must be set at "L" when the power supply is started up. (Open is prohibited.) PSIF = "H" ; Normal mode/PSIF = "L" ; Power saving mode Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The output signal is selected by LDS bit in a serial data. LDS bit = "H" ; outputs fout signal/LDS bit = "L" ; outputs LD signal Power saving mode control for the RF-PLL section. This pin must be set at "L" when the power supply is started up. (Open is prohibited. ) PSRF = "H" ; Normal mode/PSRF = "L" ; Power saving mode Charge pump output for the RF-PLL section. Power supply voltage input pin for the RF-PLL section. Ground pin for the RF-PLL section Prescaler complimentary input pin for the RF-PLL section. This pin should be grounded via a capacitor. Prescaler input pin for the RF-PLL. Connection to an external VCO should be via AC coupling. Load enable signal input pin (with the schmitt trigger circuit) When LE is set "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input pin for the 23-bit shift register (with the schmitt trigger circuit) One bit data is shifted into the shift register on a rising edge of the clock. The programmable reference divider input pin. TCXO should be connected with an AC coupling capacitor.
8
LD/fout
O
9 10 11 12 13 14
PSRF DoRF VCCRF GNDRF XfinRF finRF
I O I I
15
LE
I
16
Data
I
17 18
Clock OSCIN
I I
3
MB15F74UV
s BLOCK DIAGRAM
VCCIF GNDIF (4) (5)
PSIF (7)
SWIF
LDS
FCIF
Intermittent mode control (IF-PLL)
3 bit latch
7 bit latch
11 bit latch
Phase Fast comp. lock (IF-PLL) Tuning Charge Current pump Switch (IF-PLL)
Binary 7-bit Binary 11-bit swallow counter programmable (IF-PLL) counter (IF-PLL)
(6) DoIF
fpIF finIF (2) XfinIF (3) Prescaler (IF-PLL) (32/33, 64/65) 2 bit latch T1 T2 14 bit latch Binary 14-bit programmable ref. counter(IF-PLL) frIF OSCIN (18) Fast lock Tuning frRF T1 OR 2 bit latch finRF (14) XfinRF (13)
Prescaler (RF-PLL) (64/65, 128/129)
Lock Det. (IF-PLL) 1 bit latch C/P setting counter LDIF
AND
C/P setting counter
Selector
T2
Binary 14-bit programmable ref. counter (RF-PLL))
14 bit latch
1 bit latch LDRF fpRF Lock Det. (RF-PLL)
LD frIF frRF fpIF fpRF
(8) LD/ fout
PSRF (9)
Intermittent mode control (RF-PLL)
Binary 11-bit Binary 7-bit swallow counter programmable counter (RF-PLL) (RF-PLL)
Phase comp. (RF-PLL)
Fast lock Tuning
Charge Current pump Switch (RF-PLL)
SWRF
FCRF
LDS
(10) DoRF
fpRF
3 bit latch
7 bit latch
11 bit latch
LE (15)
Schmitt trigger circuit Schmitt trigger circuit Schmitt trigger circuit
Latch selector
Data (16) Clock(17)
CC NN 12
23-bit shift register
(1) GND
(11) (12) VCCRF GNDRF
4
MB15F74UV
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature LD/fout DoIF, DoRF Symbol VCC VI VO VDO Tstg Rating Min -0.5 -0.5 GND GND -55 Max 4.0 VCC + 0.5 VCC VCC +125 Unit V V V V C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VI Ta Value Min 2.7 GND -40 Typ 3.0 Max 3.6 VCC +85 Unit V V C Remarks VCCRF = VCCIF
Note : * VCCRF and VCCIF must supply equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF and VCCIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. * Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry has been improved in electrostatic protection, observe the following precautions when handling the device. * When storing and transporting the device, put it in a conductive case. * Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as well as yourself. Use a conductive sheet on working bench. * Before fitting the device into or removing it from the socket, turn the power supply off. * When handling (such as transporting) the device mounted board, protect the leads with a conductive sheet. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15F74UV
s ELECTRICAL CHARACTERISTICS
*
(VCC = 2.7 V to 3.6 V, Ta = -40 C to +85 C) Parameter Symbol ICCIF *1 Power supply current ICCRF *1 Power saving current finIF *3 Operating frequency finRF * finIF finRF
3
Condition finIF = 2000 MHz VCCIF = 3.0 V finRF = 2500 MHz VCCRF = 3.0 V PSIF = PSRF = "L" PSIF = PSRF = "L" IF PLL RF PLL IF PLL, 50 system RF PLL, 50 system Schmitt trigger input Schmitt trigger input VCC = 3.0 V, IOH = -1 mA VCC = 3.0 V, IOL = 1 mA VCC = 3.0 V, IDOH = -0.5 mA VCC = 3.0 V, IDOL = 0.5 mA VCC = 3.0 V VOFF = 0.5 V to VCC - 0.5 V VCC = 3.0 V VCC = 3.0 V VCC = 3.0 V, VDOH = VCC / 2, Ta = +25 C VCC = 3.0 V, VDOL = VCC / 2, Ta = +25 C CS bit = "1" CS bit = "0" CS bit = "1" CS bit = "0"
Value Min 2.1 5.7 200 2000 3 -15 -10 0.5 0.7 VCC + 0.4 0.7 VCC -1.0 -1.0 VCC - 0.4 VCC - 0.4 1.0 -8.2 -2.2 4.1 0.8 Typ 2.5 6.5 0.1 *2 0.1 *2 1.0 -6.0 -1.5 6.0 1.5 Max 3.2 8.4 10 10 2000 4000 40 +2 +2 1.5 0.3 VCC - 0.4 0.3 VCC +1.0 +1.0 0.4 0.4 2.5 -1.0 -4.1 -0.8 8.2 2.2
Unit mA mA A A MHz MHz MHz dBm dBm VP-P V V V V A A V V V V nA mA mA mA mA mA mA
IPSIF IPSRF finIF finRF fOSC PfinIF PfinRF VOSC VIH VIL VIH VIL IIH *4 IIL *4 VOH VOL VDOH VDOL IOFF IOH *4 IOL IDOH *4
OSCIN Input sensitivity
Input available voltage OSCIN "H" level input voltage "L" level input voltage "H" level input voltage "L" level input voltage "H" level input current "L" level input current Data LE Clock PSIF PSRF Data LE Clock PS
"H" level output voltage LD/ "L" level output voltage fout "H" level output voltage DoIF "L" level output voltage DoRF High impedance cutoff DoIF current DoRF "H" level output current LD/ "L" level output current fout "H" level output current DoIF *8 DoRF DoIF *8 DoRF
"L" level output current
IDOL
(Continued)
6
MB15F74UV
(Continued)
(VCC = 2.7 V to 3.6 V, Ta = -40 C to +85 C) Symbol Condition VDO = VCC / 2 0.5 V VDO VCC - 0.5 V -40 C Ta 85 C, VDO = VCC / 2 Value Min Typ 3 10 5 Max 10 15 10 Unit % % %
Parameter
IDOL/IDOH IDOMT *5 Charge pump current rate vs VDO vs Ta IDOVD *
6
IDOTA *7
*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 C, SW = "0" in locking state. *2 : VCCIF = VCCRF = 3.0 V, fosc = 12.8 MHz, Ta = +25 C, in power saving mode. PSIF = PSRF = GND VIH = VCC, VIL = GND (at CLK, Data, LE) *3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency. *4 : The symbol "-" (minus) means the direction of current flow. *5 : VCC = 3.0 V, Ta = +25 C (||I3| - |I4||) / [ (|I3| + |I4|) / 2] x 100 (%) *6 : VCC = 3.0 V, Ta = +25 C [ (||I2| - |I1||) / 2] / [ (|I1| + |I2|) / 2] x 100 (%) (Applied to both lDOL and lDOH) *7 : VCC = 3.0 V, [||IDO (+85 C) | - |IDO (-40 C) || / 2] / [|IDO (+85 C) | + |IDO (-40 C) | / 2] x 100 (%) (Applied to both IDOL and IDOH) *8 : When Charge pump current is measured, set LDS = "0" , T1 = "0" and T2 = "1".
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 VCC/2 VCC - 0.5 VCC
Charge pump output voltage (V)
7
MB15F74UV
s FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO = [ (P x N) + A] x fOSC / R fVCO : Output frequency of external voltage controlled oscillator (VCO) P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127, A < N) fOSC : Reference oscillation frequency (OSCIN input frequency) R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RFPLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually. The serial data of binary data is entered through Data pin. On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit data setting. The programmable The programmable reference counter reference counter for the IF-PLL for the RF-PLL CN1 CN2 0 0 1 0 The programmable counter and the swallow counter for the IF-PLL 0 1 The programmable counter and the swallow counter for the RF-PLL 1 1
(1) Shift Register Configuration * Programmable Reference Counter
(LSB) Data Flow (MSB)
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
18
19 20 21 22 23 X X X
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X
CS R1 to R14 T1, T2 CN1, CN2 X
: Charge pump current select bit : Divide ratio setting bits for the programmable reference counter (3 to 16,383) : LD/fout output setting bit : Control bit : Dummy bits (Set "0" or "1")
Note : Data input with MSB first.
8
MB15F74UV
* Programmable Counter
(LSB) Data Flow (MSB)
1
2
3
4 SWIF/ SWRF
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
23
CN1 CN2 LDS
FCIF/ A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 FCRF : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bits for the programmable counter (3 to 2,047) : LD/fout signal select bit : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF) : Phase control bit for the phase detector (IF : FCIF, RF : FCRF) : Control bit
A1 to A7 N1 to N11 LDS SWIF/SWRF FCIF/FCRF CN1, CN2
Note : Data input with MSB first.
(2) Data setting * Binary 14-bit Programmable Reference Counter Data Setting Divide ratio 3 4 * * * 16383 R14 R13 R12 R11 R10 R9 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 R8 0 0 * * * 1 R7 0 0 * * * 1 R6 0 0 * * * 1 R5 0 0 * * * 1 R4 0 0 * * * 1 R3 0 1 * * * 1 R2 1 0 * * * 1 R1 1 0 * * * 1
Note : Divide ratio less than 3 is prohibited. * Binary 11-bit Programmable Counter Data Setting Divide ratio N11 N10 N9 3 4 * * * 2047 0 0 * * * 1 0 0 * * * 1 0 0 * * * 1 N8 0 0 * * * 1 N7 0 0 * * * 1 N6 0 0 * * * 1 N5 0 0 * * * 1 N4 0 0 * * * 1 N3 0 1 * * * 1 N2 1 0 * * * 1 N1 1 0 * * * 1
Note : Divide ratio less than 3 is prohibited * Binary 7-bit Swallow Counter Data Setting Divide ratio 0 1 * * * 127 A7 0 0 * * * 1 A6 0 0 * * * 1 A5 0 0 * * * 1 A4 0 0 * * * 1 A3 0 0 * * * 1 A2 0 0 * * * 1 A1 0 1 * * * 1 9
MB15F74UV
* Prescaler Data Setting Divide ratio Prescaler divide ratio IF-PLL Prescaler divide ratio RF-PLL * Charge Pump Current Setting Current value CS 6.0 mA 1.5 mA 1 0 SW = "1" 32/33 64/65 SW = "0" 64/65 128/129
* LD/fout output Selectable Bit Setting LD/fout pin state LD output frIF fout output frRF fpIF fpRF LDS 0 0 0 1 1 1 1 T1 0 1 1 0 1 0 1 T2 0 0 1 0 0 1 1
* Phase Comparator Phase Switching Data Setting Phase comparator input fr > fp fr < fp fr = fp Z : High-impedance Depending upon the VCO and LPF polarity, FC bit should be set. High
(1)
FCIF, RF = "1" DoIF, DoRF H L Z
FCIF, RF = "0" DoIF, DoRF L H Z
(1) VCO polarity FC = "1" (2) VCO polarity FC = "0"
VCO Output Frequency
(2)
LPF Output voltage
Max
Note : Give attention to the polarity for using active type LPF.
10
MB15F74UV
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status Normal mode Power saving mode PS pin
H L
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes : * When power (VCC) is first applied, the device must be in standby mode. * PS pin must be set "L" at Power-ON.
OFF
ON tV 1 s
VCC Clock Data LE PS
tPS 100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON (2) Set serial data at least 1 s after the power supply becomes stable (VCC 2.2 V) . (3) Release power saving mode (PSIF, PSRF : "L" "H") at least 100 ns later after setting serial data.
11
MB15F74UV
4. Serial Data Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin. Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of the LE signal. The following diagram shows the data input timing. 1st data Invalid data 2nd data
Control bit
Data
MSB
LSB
Clock
t1 t7 t2 t3 t6
LE
t4 t5
Parameter t1 t2 t3 t4
Min 20 20 30 30
Typ
Max
Unit ns ns ns ns
Parameter t5 t6 t7
Min 100 20 100
Typ
Max
Unit ns ns ns
Note : LE should be "L" when the data is transferred into the shift register.
12
MB15F74UV
s PHASE COMPARATOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = "1")
H DoIF/RF Z L
(FC bit = "0")
DoIF/RF Z L H
* LD Output Logic IF-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state
RF-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state
LD output H L L L
Notes : * Phase error detection range = -2 to +2 * Pulses on DoIF/RF signals during locking state are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCIN input frequency as follows. tWU 2/fosc : e.g. tWU 156.3 ns when fosc = 12.8 MHz tWU 4/fosc : e.g. tWL 312.5 ns when fosc = 12.8 MHz
13
MB15F74UV
s TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
S.G. 1000 pF
50 S.G.
1000 pF
Controller (divide ratio setting)
Clock Data LE
50 OSCIN
GND S.G. 1 1000 pF finIF 50
1000 pF
18
17
16
15 14 13 finRF
VCCRF 0.1 F 1000 pF XfinRF GNDRF VCCRF
2 3
XfinIF
MB15F74UV
4 12 11 7 8 9 10
GNDIF 5 VCCIF VCCIF DoIF 6
DoRF
PSIF
LD/ fout
PSRF
0.1 F
Oscilloscope
14
MB15F74UV
s TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity vs. Input frequency
10 0 PfinRF [dBm] -10 -20 -30 -40 -50 1500
Ta = +25 C
Catalog guaranteed range
VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC
2000
2500
3000
3500
4000
4500
5000
finRF [MHz]
IF-PLL input sensitivity vs. Input frequency
10 0 PfinIF [dBm] -10 -20 -30 -40 -50 0 500 1000 1500 finIF [MHz] 2000 2500 3000
Ta = +25 C
Catalog guaranteed range
VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC
15
MB15F74UV
2. OSCIN input sensitivity
Input sensitivity vs. Input frequency
10
Input sensitivity VOSC (dBm)
0 -10 -20 -30 -40 -50 0
Catalog guaranteed range VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V SPEC
20
40
60
80
100
120
140
160
Input frequency fOSC (MHz)
16
MB15F74UV
3. RF/IF-PLL Do output current
* 1.5 mA mode IDO - VDO
2.50
Charge pump output current IDO (mA)
2.00 1.50 1.00 0.50 0.00 -0.50 -1.00 -1.50 -2.00 -2.50 0.0
VCC = 2.7 V, Ta = +25 C
0.5
1.0
1.5
2.0
2.5
3.0
Charge pump output voltage VDO (V)
* 6.0 mA mode IDO - VDO
8.00
Charge pump output current IDO (mA)
VCC = 2.7 V, Ta = +25 C
6.00 4.00 2.00 0.00 -2.00 -4.00 -6.00 -8.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Charge pump output voltage VDO (V)
17
MB15F74UV
4. fin input impedance
finIF input impedance
4 : 30.266 -102.92 773.21 fF 2 000.000 000 MHz 1 : 494.28 -874.84 200 MHz 2 : 58.094 -216.47 1 GHz 3 : 39.773 -148 1.5 GHz
1
4 3
2
START 100.000 000 MHz
STOP 2 000.000 000 MHz
finRF input impedance
4 : 20.93 -39.352 1.0111 pF 4 000.000 000 MHz 1: 37.563 -109.96 2 GHz 26.125 -71.227 3 GHz 22.848 -54.025 3.5 GHz
2:
3:
4 1 3 2
START 2 000.000 000 MHz
STOP 4 000.000 000 MHz
18
MB15F74UV
5. OSCIN input impedance
OSCIN input impedance
4 : 278.69 -1.0537 k 3.7761 pF 40.000 000 MHz 1 : 2.25 k -2.2373 k 10 MHz 2 : 881.62 -1.8299 k 20 MHz 3 : 448.75 -1.353 k 30 MHz
4 1 2 3
START 3.000 000 MHz
STOP 40.000 000 MHz
19
MB15F74UV
s REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit S.G. OSCIN Do fin Spectrum Analyzer 7.5 k VCO 0.01 F 1.6 k 0.1 F To VCO 3300 pF LPF fVCO = 2113.6 MHz VCC = 3.0 V KV = 50 MHz/V Ta = + 25 C fr = 50 kHz CP : 6 mA mode fOSC = 19.2 MHz LPF
* PLL Reference Leakage
ATTEN 10 dB RL 0 dBm VAVG 16 10 dB/ MKR -80.83 dB 50.0 kHz
MKR 50.0 kHz -80.83 dB
CENTER 2.1136000 GHz RBW 1.0 kHz VBW 1.0 kHz
SPAN 200.0 kHz SWP 500 ms
* PLL Phase Noise
ATTEN 10 dB RL 0 dBm VAVG 16 10 dB/ MKR -65.34 dB/Hz 1.00 kHz
MKR 1.00 kHz -65.34 dB/Hz
CENTER 2.11360000 GHz RBW 30 Hz VBW 30 Hz
SPAN 10.00 kHz SWP 1.92 s
(Continued)
20
MB15F74UV
(Continued)
PLL Lock Up time 2113.6 MHz2173.6 MHz within 1 kHz L chH ch 1.47 ms
A Mkr x: 439.99764 s y: 50.0009 MHz 2.173604000 GHz
2.173600000 GHz
2.173596000 GHz -500 s
2.000 ms 500 s/div
4.500 ms
PLL Lock Up time 2173.6 MHz2113.6 MHz within 1 kHz H chL ch 1.56 ms
A Mkr x: 400.00146 s y: -50.0013 MHz 2.113604000 GHz
2.113600000 GHz
2.113596000 GHz -500 s 2.000 ms 500 s/div 4.500 ms
21
MB15F74UV
s APPLICATION EXAMPLE
1000 pF
TCXO
Controller (divide ratio setting)
OSCIN Clock Data LE
OUTPUT
GND 1 1000 pF finIF XfinIF 2 3 14 13 18 17 16 15 finRF 1000 pF
OUTPUT
VCO
1000 pF
MB15F74UV
4 12 11
XfinRF GNDRF
1000 pF
VCO
GNDIF
VCCRF
LPF
VCCIF
5 6 7 8 9
LPF
VCCRF 10 DoRF PSIF LD/ fout PSRF
0.1 F
VCCIF
DoIF
0.1 F
Lock Detect
Note : Clock, Data, LE : The schmitt trigger circuit is provided (insert a pull-down or pull-up registor to prevent oscillation when open-circuit in the input) .
22
MB15F74UV
s USAGE PRECAUTIONS
(1) VCCRF and VCCIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be supplied to VCCRF and VCCIF to keep them equal. It is recommended that the non-use PLL is controlled by power saving function. (2) To protect against damage by electrostatic discharge, note the following handling precautions : * Store and transport devices in conductive containers. * Use properly grounded workstations, tools, and equipment. * Turn off power before inserting or removing this device into or from a socket. * Protect leads with conductive sheet, when transporting a board mounted device
s ORDERING INFORMATION
Part number MB15F74UVPVB Package 18-pin plastic BCC (LCC-18P-M05) Remarks
23
MB15F74UV
s PACKAGE DIMENSION
18-pin plastic BCC (LCC-18P-M05)
2.31(.090) TYP 0.45(.018) TYP.
15
2.700.10 (.106.004)
10
0.450.05 (.018.002) (Mount height)
10
15
INDEX AREA
2.400.10 (.094.004)
2.01(.079) TYP 0.45(.018) TYP. 0.0750.025 (.003.001) (Stand off) "A" "C" "B"
0.90(.035) REF 1.90(.075) REF
1
6
6
1.35(.053) REF 2.28(.090) REF
1
Details of "A" part 0.05(.002) 0.14(.006) MIN. 0.250.06 (.010.002)
Details of "B" part C0.10(.004) 0.360.06 (.014.002)
Details of "C" part 0.360.06 (.014.002)
0.250.06 (.010.002)
0.280.06 (.011.002)
0.280.06 (.011.002)
C
2003 FUJITSU LIMITED C18058S-c-1-1
Dimensions in mm (inches) Note : The values in parentheses are reference values.
24
MB15F74UV
FUJITSU LIMITED
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F0401 (c) FUJITSU LIMITED Printed in Japan

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